The present invention relates to a nonvolatile semiconductor memory device having memory cells allowing an electrical data write and erase.
Conventionally, a flash memory which can be erased in blocks has received a great deal of attention as one of electrically programmable and erasable read only memories (EEPROMs) which are classified as one of nonvolatile semiconductor memories. The flash memory cell has a MOS transistor structure wherein a floating gate insulated from the peripheral region is formed between the control gate and the substrate having the channel. Discrimination between data of level "1" and data of level "0" depends on the presence/absence of charges in the floating gate.
FIGS. 8A and 8B show such a flash memory cell having a transistor structure wherein a channel region is formed around the side wall of a vertical silicon column.
In this flash memory cell, a columnar portion (pillar) 1102 is formed on a p-type semiconductor substrate 1101. A drain 1103 is formed at the upper portion of the pillar 1102, and a source 1104 is formed in the semiconductor substrate 1101 under the pillar 1102.
A floating gate 1106 is formed on the side wall of the pillar 1102 via a gate insulating film 1105. A control gate 1108 is formed around the floating gate 1106 via an insulating film 1107. An interconnection 1110 as a bit line is connected to the drain 1103 through an insulating interlayer 1109.
When the source and the drain are formed under and at the upper portion of the columnar portion, respectively, and the floating gate and the control gate are formed on the side wall portion of the columnar portion, the two-dimensional size of the cell can be reduced while increasing the read current, so the degree of integration of the memory cell can be improved.
In the above-described vertical-type flash memory cell, however, only "0" or "1" can be stored in one memory transistor. To increase the amount of information to be stored, the number of memory cells must be increased, so the degree of integration cannot increase.
Conventionally, a technique of realizing multilevel data by a circuit operation is used. Such a technique realizes, e.g., quarternary data by changing the amount of charges stored in the floating gate.
In this case, however, the number of power supplies necessary for realizing multilevel data increases to result in a heavy load on, e.g., a charge pump circuit. The necessity for such a circuit also impedes high integration.
Additionally, to realize multilevel data by the circuit operation, a threshold value range per level must be considerably narrow. For this reason, the amount of charges to be injected into the floating gate must be strictly controlled to result in an increase in load on the controller or write time. This narrow threshold value range also imposes limitations on the margin to a change over time in data holding characteristics to lower reliability. More specifically, when the held charge amount changes along with the elapse of time, the read current changes accordingly, and a data value different from that stored is read.